1. Field of the Invention
The field of the invention relates to semiconductor processing, particularly parasitic paths resulting from stingers.
2. Prior art
During the fabrication of semiconductor devices, overhangs or crevices are sometimes formed in integrated circuit structures. For instance, etching and/or the formation of insulative regions may result in the formation of overhangs, crevices, or the like (hereinafter collectively referred to as overhangs). A subsequently formed conductive layer may be deposited within the overhangs. When this conductive layer is etched with an anisotropic etchant to define a circuit element for the integrated circuit, portions of the layer (referred to as "stringers") may remain within the overhangs. Stringers often define parasitic paths harmful to the operation of the integrated circuit.
One method for removing stringers is to alter the chemistry of an anisotropic etch at or near its end point to make it more isotropic. The conductive material within the overhang is etched as the etching becomes more isotropic. This is described in "Multi-Etchant Loading Effect and Silicon Etching in ClF.sub.3 and Related Mixtures", by Flam, Wang and Maydan, Journal of Electrochemical Society: Solid-State Science and Technology, December 1982, beginning at page 2755. Also see U.S. Pat. No. 5,071,265. One problem with this technique is that the critical dimensions are altered when the isotropic etching occurs. Another process for dealing with stringers is described in U.S. Pat. 4,536,947, FIGS. 11-14.
The formation of stringers often occurs where two layers of polysilicon are used. One process with two layers of polysilicon is used to fabricate electrically programmable memory arrays where each memory cell has a floating gate. In this well-known process, first parallel spaced-apart lines are formed from a first layer of polysilicon. Then from a second layer of polysilicon, insulated from the first lines, second parallel spaced-apart lines are formed, at right angles to the first lines. Following this, the first lines are etched in alignment with the second lines to form the floating gates from the first lines. The second lines become the word lines in the memory array. Numerous other fabrication steps for the memory array are omitted from this discussion. Formation of memory cells and arrays using this processing are described in U.S. Pat. Nos. 4,142,926 and 4,780,424.
In this process stringers can result from fragments of the second polysilicon layer especially where the first layer of polysilicon is initially etched after the etching of the dielectric used between the first and second layers. These stringers reside in overhangs formed in the bases of the first polysilicon lines. Conductive paths between adjacent word lines caused by these stringers render the array inoperative. This problem will be discussed in more detail in conjunction with the figures.
The present invention is described in conjunction with eliminating the effects of the stringers while fabricating a memory array using two layers of polysilicon.